Hi maehne, thank you very much for the answers. 1) Yes, my time step is set in srcs (Tm_ = 1e-9) and the expected cut-off frequency is approximately 2MHz. 2) I was able to find the expected cutoff frequency with good accuracy, even with the TDF-> DE domain conversion ports, but I will change to achieve better results as you indicated !! The error was in my analysis, because the input sinusoid had an off set DC which changes the shape to find the cutoff frequency, but I have already solved it. 3) Yes I will follow the instructions to use the recommended headers.
Hello everyone, I'm performing the verification of a simple Sample and Hold implemented in SystemC-AMS. The Sample and Hold is modeled with the MOC ELN, the MOC TDF input signal source, and Sample and Hold output a port for the discrete domain. When the sample switch is closed for a long time the circuit has a low pass filter behavior, so the check consists of finding the cut-off frequency in this situation through the voltage gain (v_out / v_in = 0.707). However, this gain is only being achieved with frequencies much larger than the cutoff frequency. Codes are shown below Can anyone help? The