uvm_monitor and class parameter

[verif_learner]

is it common not to have uvm_monitor without parameter?

For example, the following is a snippet from uvm reference guide. The monitor does not have any parameter while driver has user defined sequence_item as a parameter

class master_monitor extends uvm_monitor;
virtual bus_if xmi; // SystemVerilog virtual interface
bit checks_enable = 1; // Control checking in monitor and interface.
bit coverage_enable = 1; // Control coverage in monitor and interface.

 

class simple_driver extends uvm_driver #(simple_item);
 simple_item s_item;
 virtual dut_if vif;
 // UVM automation macros for general components
 `uvm_component_utils(simple_driver

Does this mean that I cannot have multiple instances of monitor with different sequence_item types as class is not type parameterized?