Roman Popov Posted January 11, 2018 Report Share Posted January 11, 2018 In SystemVerilog there is a standard interface keyword for module-like interface structures. Main purpose of interfaces is grouping of ports, protocol handling logic and assertions together. In SytemC there is no standard one in a language. Because of this each vendor has it's own way to create interfaces: some use pragmas, others special MACRO. In some tools interface is a class derived both from sc_module and sc_interface. There are two typedefs in a SystemC library: typedef sc_module sc_channel; typedef sc_module sc_behavior; Was it supposed that one of these should be used for interface classes? Quote Link to comment Share on other sites More sharing options...
vishwap Posted January 12, 2018 Report Share Posted January 12, 2018 I don't remember if the concept of interface came first in SystemC or SystemVerilog. But the interfaces are pretty much there in SystemC. Look at sc_interface. You can define your own interface class my_interface : public sc_interface { // ports and methods } then you can use this interface to define ports like this. class my_module : public sc_module { ........ sc_port<my_interface> myPort; } And the you can define your channels which you can use to connect this new type of ports. This I am just giving a rough idea. There are some examples available in the distribution. Quote Link to comment Share on other sites More sharing options...
Roman Popov Posted January 12, 2018 Author Report Share Posted January 12, 2018 17 minutes ago, vishwap said: You can define your own interface class my_interface : public sc_interface No, this is not how interface in SystemVerilog works. Your example is more like Java or C# interface. Quote Link to comment Share on other sites More sharing options...
David Black Posted January 12, 2018 Report Share Posted January 12, 2018 Java / C# interface is precisely what SystemC interface is. Your original question was more about port aggregation. The problem is that Verilog ports are really quite a different concept. To be sure , there are superficial similarities, SystemC is not an HDL. Mind you, it is quite easy to aggregate SystemC ports. Just define an aggregate class derived from sc_port. This would also allow you to crate aggregate methods (I.e. beyond simple bind). Just don’t expect this to be useable in synthesis. Perhaps a savvy EDA vendor will pickup on This if there is sufficient commercial interest, which I doubt. Quote Link to comment Share on other sites More sharing options...
Roman Popov Posted January 14, 2018 Author Report Share Posted January 14, 2018 Perhaps a savvy EDA vendor will pickup on This if there is sufficient commercial interest, which I doubt. Well, actually all HLS tools I've used have notion of modular interfaces. I.e. special kind of modules that aggregate ports together with protocol-handling threads and methods. For example in C-to-Silicon compiler you have to derive from both sc_module and sc_interface to create an interface module: struct slave : sc_module , sc_interface { sc_in<bool> data_rdy{"data_rdy"}; sc_in<int> data{"data"}; sc_out<bool> ack{"ack"}; sc_port<slave_if> slave_port{"slave_port"} ... }; The problem is that every tool has it's own way to define this concept. This seem to me like a language design issue: Why not standardize a common keyword for this concept? Quote Link to comment Share on other sites More sharing options...
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