uvm_reg usage with virual sequencers

[aluri20]

Hi,

I my testbench environment contains an APB UVC and couple of other UVC. I am trying to implement UVM_reg model to verify the register map. is there an example of how to create a register model and integrate and control using virtual sequencer ?

Thanks

[amitshere]

In your virtual sequence, you will need to create the sequence using uvm_create() then make the appropriate regmodel assignment and then start the sequence using seq.start()