aluri20 Posted December 23, 2011 Report Share Posted December 23, 2011 Hi, I my testbench environment contains an APB UVC and couple of other UVC. I am trying to implement UVM_reg model to verify the register map. is there an example of how to create a register model and integrate and control using virtual sequencer ? Thanks Quote Link to comment Share on other sites More sharing options...
amitshere Posted January 3, 2012 Report Share Posted January 3, 2012 In your virtual sequence, you will need to create the sequence using uvm_create() then make the appropriate regmodel assignment and then start the sequence using seq.start() Quote Link to comment Share on other sites More sharing options...
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.