Shobhana soni Posted November 7, 2017 Report Posted November 7, 2017 In UVM phases phases provide synchroniztion between components but in systemverilog it's not like that what makes it difficult for sv as they are not having phases Quote
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.