tjwang0709 Posted August 27, 2017 Report Share Posted August 27, 2017 Dear all, Maybe this question has been asked before. If so, I am sorry to ask it again, and please let me know the post. This is a question about UVM-1.2 in SystemVerilog. I am studying the UVM source code provided by VCS. In uvm-1.2/src/tlm2/uvm_tlm2_sockets.svh, class uvm_tlm_nb_passthrough_initiator_socket#(T,P) has function void connect(this_type provider); uvm_tlm_nb_passthrough_initiator_socket_base #(T,P) initiator_pt_socket; ... ... if($cast(initiator_pt_socket, provider)) begin bw_export.connect(initiator_pt_socket.bw_export); return; end A question about this function is: Should the line bw_export.connect(initiator_pt_socket.bw_export); be initiator_pt_socket.bw_export.connect(bw_export); instead ? That is, could anyone help to explain why the direction of the above connection is opposite to the direction of the other two connections ( shown below ) in the same function ? if($cast(target_pt_socket, provider)) begin target_pt_socket.bw_port.connect(bw_export); return; end if($cast(target_socket, provider)) begin target_socket.bw_port.connect(bw_export); return; end Thanks. Quote Link to comment Share on other sites More sharing options...
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