Erling Posted December 8, 2011 Report Share Posted December 8, 2011 Given a large design with multiple generated sub-designs with mostly low traffic signalling between them, is there reason to believe that it would help speed up the simulation by running each sub-design in its own uvm environment and have the signalling between them go through some sort of inter process(or) communication? Are there solutions in existence (or planned) for implementing such a distributed testbench over cores or even a network of computers? Erling Quote Link to comment Share on other sites More sharing options...
sacjin1123 Posted December 22, 2011 Report Share Posted December 22, 2011 you can use virtual sequencer and virtual sequence to make synchronization between the different environment. Quote Link to comment Share on other sites More sharing options...
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.