Erling 1 Report post Posted December 8, 2011 Given a large design with multiple generated sub-designs with mostly low traffic signalling between them, is there reason to believe that it would help speed up the simulation by running each sub-design in its own uvm environment and have the signalling between them go through some sort of inter process(or) communication? Are there solutions in existence (or planned) for implementing such a distributed testbench over cores or even a network of computers? Erling Quote Share this post Link to post Share on other sites
sacjin1123 0 Report post Posted December 22, 2011 you can use virtual sequencer and virtual sequence to make synchronization between the different environment. Quote Share this post Link to post Share on other sites
