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Design of a 32 bit input for a system and deconstruct it into individual bits


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I have a simple project it's goal is to create a 32 bit ripple adder from an array of Full adders (FA).

I have successfully implemented the FA (implementation attached) , but I have a simple problem now.

Unlike the FA , the Ripple adder has many more inputs, and I cant find an efficient way to model these inputs , for instance in VHDL I would have an input port with the number of bits that I needed and I can access them easily in the architecture of the module, Unfortunatly this isn't the case for me in systemC.

Approaches that I tried include:

  • Using ( sc_in<sc_lv<32>> ) , which seems logical , but I cant deconstruct the vector into sc_logic inputs  that I can then pass to my FA sub-modules to process.
  • using ( sc_lv::read() ), doesn't seems to output the right data type (sc_logic) , I even tried type casting, but the constructor for the FA failed.
Using array of sc_in<sc_logic> *A[32],*B[32]; , this approach is probably the closest I have got, It compiles correctly , but it doesn't run as there is always some kind of port that isn't connected correctly.

Basically , I need to know how to model a 32 bit module and pass each individual bit to their respective sub-module.

I know that there is the approach of declaring 32 inputs individually, but this seems tedious and the language must have some better approach. 

I realize this might seems easy, but I'm still new to systemC , and would love for someone to give me their feedback on how to implement this Ripple Adder as it would help me immensely in my project.





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