Hi,
I have a simple project it's goal is to create a 32 bit ripple adder from an array of Full adders (FA).
I have successfully implemented the FA (implementation attached) , but I have a simple problem now.
Unlike the FA , the Ripple adder has many more inputs, and I cant find an efficient way to model these inputs , for instance in VHDL I would have an input port with the number of bits that I needed and I can access them easily in the architecture of the module, Unfortunatly this isn't the case for me in systemC.
Approaches that I tried include:
Using ( sc_in<sc_lv<