Read Memory Acess Violation

[SysC_Lrnr]

Hi,

In the following header file many sub modules are connected to a top module of sc_vector ports.

The file builds fine, but on running a window message "...has stopped".

Debugging figured out:

A thrown exception "read access violation ";

The line precedes it in the call stack (the one commented beside it in the code ), includes binding a sub module port to one of the top-module's vectors' port.

Also note the exception is thrown after one complete iteration of the for loop (i.e. j =1)

Does this have anything to do with my initialization to the port vectors?

#pragma once
#include "systemc.h"
#include "ArrMult_Unit.h";

SC_MODULE(ArrMult_32)
{
	//Ports
	sc_vector < sc_in < sc_logic > >  xi;
	sc_vector < sc_in < sc_logic > >  yi;
	sc_vector < sc_in < sc_logic > >  R;

	//
	sc_signal < sc_logic> x_sig[32];
	sc_signal < sc_logic> y_sig[32];
	sc_signal < sc_logic> s    [16][16];
	sc_signal < sc_logic> co   [16][16];
	sc_signal < sc_logic> GND;
	sc_signal < sc_logic> Dummy;

	//

	ArrMult_Unit *unit[16][16];
	
	SC_CTOR(ArrMult_32)
		:xi("xi",32), yi("yi", 32),R("R", 32)
	{

		for (int i = 0;i < 16;i++)
		{
			for (int j = 0;i < 16;i++)
			{
				char Unit_Name[20];
				sprintf(Unit_Name, "ArrMult_Unit_%d%d", i, j);
				unit[i][j] = new ArrMult_Unit(Unit_Name);
				xi[i].size();
			}
		}

		GND = SC_LOGIC_0;


		for (int j = 0;j < 16;j++)
		{
			unit[0][j]->w(xi[j]);// The line after which an exception was thrown
			unit[0][j]->op2i(yi[j]);
			unit[0][j]->op1(GND);
			unit[0][j]->cin(GND);
			unit[0][j]->sum(s[0][j]);
			unit[0][j]->cout(co[0][j]);

		}

...
};

 

[ralph.goergen]

Hi.

You cannot have C-style arrays of SystemC objects. This includes ports, modules, and *signals*.

Use sc_vector instead.

BTW: I think it should be possible to drop an sc_vector in an sc_vector to realize two dimensions.

Greetings

Ralph

[AmeyaVS]

Hello @SysC_Lrnr,

@ralph.goergen is right you need to use sc_vector's for SystemC objects.

Also use C++ built-in datatype's (bool, char, short int, int, etc.) to have better performance and better compiler optimizations.

For small designs you would not feel the need but as you would add complexity to your SystemC simulation models you'll start noticing the difference.

Regards,

Ameya Vikram Singh

[SysC_Lrnr]

Thanks Ralph and Ameya.

I really appreciate your help.