Akhila Posted February 10, 2017 Report Share Posted February 10, 2017 Hi All, Just wanted to check if the UVM sequence macros (UVM_DO_ON_WITH and UVM_DO_WITH) which support randomizing the sequence object are yet supported by UVM-SC or not? If not, what is the best way to add some randomization in the framework? I saw a post where there are some snippets (link given below) using scvx_rand_object class but I am not sure where to find this(didn't find it in latest SCV and UVM-SC libraries). http://nascug.org/events/20th/1-NASCUG20-UVMforSystemC-Karsten.pdf Also, I get errors while using plain UVM_DO_ON macros. Is it expected? The same works fine with ahb_wr_seq->start(top_env->agent->ahb_sequencer_inst); I have registered the sequence class with factory already. UVM_DO_ON(ahb_wr_seq,top_env->agent->ahb_sequencer_inst); Error message says: /nfs/iind/disks/ba_bdl_xplore_disk001/am5/UVM_SC/uvm-systemc-1.0-alpha1/src/uvmsc/macros/uvm_sequence_defines.h:150:31: error: expected type-specifier before ‘typeof’ SEQ_OR_ITEM = dynamic_cast< typeof(SEQ_OR_ITEM) >(create_item(objw__, SEQR, "SEQ_OR_ITEM")); ^ /nfs/iind/disks/ba_bdl_xplore_disk001/am5/UVM_SC/uvm-systemc-1.0-alpha1/src/uvmsc/macros/uvm_sequence_defines.h:115:3: note: in expansion of macro ‘UVM_CREATE_ON’ UVM_CREATE_ON(SEQ_OR_ITEM, SEQR) \ ^ /nfs/iind/disks/ba_bdl_xplore_disk001/am5/UVM_SC/uvm-systemc-1.0-alpha1/src/uvmsc/macros/uvm_sequence_defines.h:80:3: note: in expansion of macro ‘UVM_DO_ON_PRI_WITH’ UVM_DO_ON_PRI_WITH(SEQ_OR_ITEM, SEQR, -1, "") ^ ahb_basic_test.h:59:11: note: in expansion of macro ‘UVM_DO_ON’ UVM_DO_ON(ahb_wr_seq,top_env->agent->ahb_sequencer_inst); Appreciate any help here. Thanks Akhila Quote Link to comment Share on other sites More sharing options...
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