tudor.timi Posted June 23, 2016 Report Share Posted June 23, 2016 As per section E.6.3.6 Numbers, only formats legal in SystemVerilog are allowed for constants. The sample XML in annex I.5 contains the numbers "0x40000000" and "0x1000" which aren't legal SystemVerilog constants. Quote Link to comment Share on other sites More sharing options...
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