Jump to content

Recommended Posts

Posted

Hello Sir,

 

Thanks for reply.

 

1. It is SystemC reference model.

2. This SystemC reference model need to be verified in UVM-SV testbench.

3. Now my doubt is how to connect this SystemC reference model with the UVM-SV testbench. Both are ready at my end. Here SystemC reference model act as RTL and UVM-SV testbench act as testbench environment for this reference model.

4. Testcases are written in UVM-SV testbench.

 

Pleasse guide me in this regard. Since i am new to SystemC and integration.

 

Regards

Sunil S. 

Posted

Hello Gerth,

 

It is ModelSim-10.2b simulator. And i am in need of single script that simulate both SystemC and UVM-testbench. Actually i am not able to address both environment via a single script. Please Guide.

 

 

Regards

Sunil S.

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...