susharmas Posted April 19, 2016 Report Posted April 19, 2016 Hello Sir, Can you please guide me how to connect the SystemC RTL model and UVM testbench. Please help in this regard. Regards Sunil S. Quote
Martin Barnasconi Posted April 19, 2016 Report Posted April 19, 2016 Please further explain your question: A system-level in SystemC model is often at a higher abstraction than RTL. Do you mean a UVM-SV or UVM-SystemC testbench? Please have a look if your answer is in this FAQ http://www.accellera.org/activities/working-groups/systemc-verification/uvm-systemc-faq Quote
susharmas Posted April 20, 2016 Author Report Posted April 20, 2016 Hello Sir, Thanks for reply. 1. It is SystemC reference model. 2. This SystemC reference model need to be verified in UVM-SV testbench. 3. Now my doubt is how to connect this SystemC reference model with the UVM-SV testbench. Both are ready at my end. Here SystemC reference model act as RTL and UVM-SV testbench act as testbench environment for this reference model. 4. Testcases are written in UVM-SV testbench. Pleasse guide me in this regard. Since i am new to SystemC and integration. Regards Sunil S. Quote
Stephan Gerth Posted April 20, 2016 Report Posted April 20, 2016 Hi Sunil, the integration of a SystemC model and a UVM-SystemVerilog testbench is dependent on your SV-simulator which is why you should address your EDA-vendor about that. Stephan Quote
susharmas Posted April 20, 2016 Author Report Posted April 20, 2016 Hello Gerth, It is ModelSim-10.2b simulator. And i am in need of single script that simulate both SystemC and UVM-testbench. Actually i am not able to address both environment via a single script. Please Guide. Regards Sunil S. Quote
Stephan Gerth Posted April 20, 2016 Report Posted April 20, 2016 Hi Sunil, as said before: I can't provide you support for your EDA tool. Please address your vendor for that. Quote
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