virtual sequencer exit main phase prematurely

[Ed Jone]

hi all, 

 

  my SPI test stuck and test sequence is hung on wait_for_grant(). 

 

  I turned the verbosity to UVM_DEBUG and found out virtual sequencer and physical sequencer exit from main phase and directly go to post_shutdown phase. 

 

that is why when my test sequence called wait_for_grant(), the sequencer is not there. 

 

any suggestion or comment is appreciated. 

 

Thank you. 

 

Ed

 

below is the test log.

 

 

@24279670 [spi_m_driver] spi_m_driver:Drive got item from sequencer : ----------------------------------------------------------------------------------------------------

  sequencer                    string           46    uvm_test_top.env.spi_mst_agent.spi_m_sequencer

@24279670 [spi_m_driver] spi_m_driver:Master started driving clock

@24279670 [spi_m_driver] spi_m_driver:drive_packet called driving packet

@24279670 [spi_m_driver] spi_m_driver:sample_packet method starts

@25689150 [spi_m_driver] spi_m_driver:drive_packet completed

@25689150 [spi_m_driver] spi_m_driver:sample_packet method ends

@25689150 [spi_m_driver] spi_m_driver:get_and_drive setting seq_item_port.item_done

@25689150 [spi_m_driver] spi_m_driver:get_and_drive completed

@25689150 [spi_m_driver] spi_m_driver:get_and_drive started

@25689150 [spi_m_driver] spi_m_driver: columbo inserting 1 clocks in between spi transactions

@25689150 [spi_m_driver] spi_m_driver: 1 clocks in between spi transactions gap done

@25689150 [spi_m_driver] spi_m_driver:waiting for async reset

@25689150 [spi_m_driver] spi_m_driver:Waiting for sequence item

@25689150 [RegModel] reporter:Wrote register via map reg_model.spi_map: reg_model.bank0.TEST_MODES=0x4

@25689150 [PHASESEQ] v_seq:No default phase sequence for phase 'post_main'

@25689150 [PHASESEQ] spi_m_sequencer:No default phase sequence for phase 'post_main'

@25689150 [PHASESEQ] v_seq:No default phase sequence for phase 'pre_shutdown'

@25689150 [PHASESEQ] spi_m_sequencer:No default phase sequence for phase 'pre_shutdown'

@25689150 [PHASESEQ] v_seq:No default phase sequence for phase 'shutdown'

@25689150 [PHASESEQ] spi_m_sequencer:No default phase sequence for phase 'shutdown'

@25689150 [PHASESEQ] v_seq:No default phase sequence for phase 'post_shutdown'

@25689150 [PHASESEQ] spi_m_sequencer:No default phase sequence for phase 'post_shutdown'

@26900328 [spi_m_driver] spi_m_driver:SPI update configuration started

@26900328 [spi_m_driver] spi_m_driver:SPI update configuration completed

@26900328 [mem_rw:SPI_MEMORY_RW_START] spi_m_sequencer@@mem_rw:Starting spi_memory_rw sequence

@26900328 [burst_write:SPI_BURST_WRITE_START] burst_write:Starting spi_burst_write sequence

@26900328 [burst_write:SPI_BURST_WRITE_START] burst_write:p_sequencer : 010A89

@26900328 [burst_write:SPI_BURST_WRITE_START] burst_write:m_sequencer : 010A89

@26900328 [burst_write:SPI_BURST_WRITE_START] burst_write:wait_for_grant

 

 

[mastrick]

I believe you want your test sequence to object to main_phase so that you will not have the physical sequence ended before the test sequence ends.