Jump to content

Issue with bit width for double and float types in VCD tracing

Stephan Gerth

Recommended Posts

A VCD tracing of a sc_signal<double> generates to following line in the resulting file: 

$var real    1  aaaaa  dbl_s       $end

The vcd2wlf tool of Mentor now chokes on that (I tested version 10.4) when the value of aaaaa is set:

r30000000000 aaaaa

(This was no problem for e.g. version 10.1d).


If I understand it correctly, the definition of aaaaa says that it is only one bit in size which is obviously no the intention here. When changing sc_vcd_trace.cpp:1589 to

bit_width = 64;

I get the following line in the VCD which then poses no problem for vcd2wlf anymore as the bit width is now correct:

$var real   64  aaaaa  dbl_s [63:0]  $end

The same problem applies for signals of type float (where changing line 1553 in the same file accordingly apparently solves the issue).


Is there any particular reason why the bit widths for those types are set to '1'? For a real bugfix I guess the bit width should be set to something derived from a sizeof operation.


Link to post
Share on other sites

Hi Stephan,

I am not sure you have to specify the bit width for real's as the format seems to be fixed to double precision. Also you cannot dump part of a vector so the bit width is redundant.

This is what I picked up from the LRM:

A real number is dumped using a %.16g printf() format. This preserves the precision of that number
by outputting all 53 bits in the mantissa of a 64-bit IEEE Std 754-1985 [b1] double-precision number.
Application programs can read a real number using a %g format to scanf().

I might be wrong of couse, you could raise an SR with Mentor to see what they have to say,

Good luck,

Link to post
Share on other sites
  • 2 weeks later...


This topic is now archived and is closed to further replies.

  • Create New...