qubits1 Posted January 13, 2016 Report Share Posted January 13, 2016 I have a design in vhdl and I'm trying to use systemc-uvm verification library. Since I've a single language vhdl license on modelsim, I was wondering if I could use g++ for the verification side and cosimulate with modelsim? If so, how would I do this? I'm not sure how to connect the my testbench to the dut. Could you point me to some example code for making this connection and running the sim? Thanks in advance Quote Link to comment Share on other sites More sharing options...
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