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systemc testbench cosimulation with vhdl in modelsim

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I have a design in vhdl and I'm trying to use systemc-uvm verification library. Since I've a single language vhdl license on modelsim, I was wondering if I could use g++ for the verification side and cosimulate with modelsim? If so, how would I do this?


I'm not sure how to connect the my testbench to the dut. Could you point me to some example code for making this connection and running the sim?



Thanks in advance

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As stated in the FAQ UVM-SystemC does not support multi-language, and we advice you to contact your local EDA solution provider to check if UVM-SystemC can be combined with your RTL design.


There are other initiatives and libraries to address the multi-language challenge. I would also advice you to contact your local EDA solution provider for this.

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It should be possible but will definitely hard without the VHDL/SystemC cosimulation option.


Without cosimulation, what basically remains is a VHDL simulation that should be connected to a C++ program. Modelsim offers the Foreign Language Interface (FLI) for things like that. But, you will have to implement the entire cosimulaiton part (synchronization, data conversion and exchange, ...) by yourself.




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