c4brian Posted October 14, 2015 Report Share Posted October 14, 2015 I have an untimed, event driven systemC model inside of a SystemVerilog UVM environment. At time .000150, an actual transaction is detected on the bus, and send to the scoreboard. The transaction from the SystemC model also comes at the exact same time, but they all cause the UVM reporting to say 0 time, I'm guessing because the SystemC never advances the simulation time (purely event driven), while the SV-side keeps chugging along. Functionally there is no issue, but the reports are extremely confusing: # KERNEL: UVM_INFO @ 0.000150 ms | uvm_test_top.env.PlbSb | SCOREBOARD | Act Txn FIFO Written (# 0): Op:PLB_READ_MEM - addr:0 - data:0xf477a934 - CS_sel:0 # UVM_INFO @ 0.000000 ms | uvm_test_top.env.plb_hub | plb_socket_hub | Sending exp transaction to SB... # KERNEL: UVM_INFO @ 0.000000 ms | uvm_test_top.env.PlbSb | SCOREBOARD | Exp Txn FIFO Written (# 0): Op:PLB_READ_MEM - addr:0 - data:0xf477a934 - CS_sel:0 Does anyone understand how the "simulation time" thread(s) are handled between SV and SC? It appears they both have their own simulation time, and they are completely independent. Thoughts? This is the run_phase of a component which generated the above prints. As soon as it returns from the b_transport to the SystemC model, all UVM prints have a time of 0. it's like it "snagged" the simulation time from the SystemC model, and is using that now. forever begin fifo.get(txn); // receive a transaction from agent `uvm_info(report_id, $sformatf("Got an input txn: %0s", txn.convert2string()), UVM_DEBUG) out.b_transport(txn,delay); // Returning from here... UVM thinks the sim time is 0 ns! ack... t_copy = plb_transaction::type_id::create("t_copy"); t_copy.copy(txn); `uvm_info(report_id, "Sending exp transaction to SB...", UVM_DEBUG) sb_out.write(t_copy); // broadcast expected transaction end Quote Link to comment Share on other sites More sharing options...
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