System Verilog wrapper for VHDL DUT

[jao16]

Hello

I am building a simple UVM Tbench for a VHDL DUT.

QS: How to write the System Verilog wrapper for the VHDL DUT to interface to the UVM test bench?

Any pointers would be much appreciated.

Thanks

JO

[mrmikehicks]

JO, I'm probably only a few pages ahead of you, but look at the attached file set. It includes a CPLD (Xilinx 9536) design in VHDL interfaced to the SV testbench (taken from UVM examples.) The CPLD has a very simple structure. It receives a bit-banged command and either sets/clears bits in a 7 bit output port, or it sends a 4 bit command to a 4 bit display output port with some write logic, and then returns an ACK signal.

I searched hi and low for an example that would show any structure that included a VHDL DUT and a UVM/OVM/AVM/VMM and a few other verification suites, but found none. Using a combination of answers I received on this forum and other examples on the net, I came up with this format, which works for me. I can monitor and wiggle the pins on my VHDL DUT through the SystemVerilog bench. The purest out there will probably indicate that I could have done it better 'this way' or 'that' but this is what works. There are also probably real examples out there somewhere, but again, I couldn't find them.

Most of the answers I receive on the various verification forums are 'close, but no cigar'. I'm beginning to see a common thread in these forums, that espouses the theory that 'this Verilog and SystemVerilog stuff is all so simple, I won't even bother to explain it in detail', and so they don't.

Anyway, I hope this example file set leads you to a solution that works for you.

Mike[ATTACH]33[/ATTACH]

[jao16]

Hello Mike

Thank you very much for the examples you sent.

This will help greatly.

Best regards

JO

[poorvaag]

Hello Mike

 

Could you attach the examples again? I am faced with a similar problem and not able to see the attachment in the current post.

 

Thanks much!

 

PA