jao16 Posted October 4, 2011 Report Share Posted October 4, 2011 Hello I am building a simple UVM Tbench for a VHDL DUT. QS: How to write the System Verilog wrapper for the VHDL DUT to interface to the UVM test bench? Any pointers would be much appreciated. Thanks JO Quote Link to comment Share on other sites More sharing options...
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