jstahl Posted August 10, 2015 Report Share Posted August 10, 2015 Hi, I'm very interested in trying out uvm-systemc and heard it would be available on Github this summer. I was wondering if someone could let me know the current status ? Thanks, Jon Quote Link to comment Share on other sites More sharing options...
Martin Barnasconi Posted August 15, 2015 Report Share Posted August 15, 2015 The Accellera SystemC Verification Working Group is working hard to make a stable release of the UVM-SystemC library and Language Reference Manual. Standardization of the API is still ongoing and there are still changes proposed to both library as well as LRM. As soon as things are getting stable, we will consider releasing it. Timing will be defined by the Accellera VWG. Quote Link to comment Share on other sites More sharing options...
brucezhan Posted November 18, 2015 Report Share Posted November 18, 2015 Any progress about the releasing time? Quote Link to comment Share on other sites More sharing options...
Stephan Gerth Posted November 19, 2015 Report Share Posted November 19, 2015 Yes, it was announced at DVCON that there will be an alpha release soon. This currently focusses on end of next week. Quote Link to comment Share on other sites More sharing options...
brucezhan Posted November 19, 2015 Report Share Posted November 19, 2015 Thank you very much. I'd like to try it in my coming project. Quote Link to comment Share on other sites More sharing options...
angel Posted November 20, 2015 Report Share Posted November 20, 2015 Hi, there are two packages available to play around, UVM_ML_OA from Cadence http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ and UVMC from Mentor, https://verificationacademy.com/verification-methodology-reference/uvmc-2.3.0/docs/html/files/docs/OVERVIEW-txt.html I have tried both and both are quite similar, but I would start with the Mentor solution ,it is better docmented Cheers And have fun!!! Angel Quote Link to comment Share on other sites More sharing options...
brucezhan Posted November 20, 2015 Report Share Posted November 20, 2015 My situation might be a little different. I need to run the testbench with FPGA and I don't want to involve vcs or mentor tools in. Quote Link to comment Share on other sites More sharing options...
Roman Popov Posted November 29, 2015 Report Share Posted November 29, 2015 Hi, According to http://accellera.org/activities/working-groups/systemc-verification : The UVM-SystemC Library was released in November 2015 as a public review release. But there is no download link anywhere on accellera portal. Where can I get public release? Quote Link to comment Share on other sites More sharing options...
Stephan Gerth Posted December 2, 2015 Report Share Posted December 2, 2015 Hi Roman, that's true. The part is already removed as we didn't make it until end of last week for various reasons. However, currently we are trying hard to release it by end of this week now. Quote Link to comment Share on other sites More sharing options...
Roman Popov Posted December 2, 2015 Report Share Posted December 2, 2015 Hi Roman, that's true. The part is already removed as we didn't make it until end of last week for various reasons. However, currently we are trying hard to release it by end of this week now. Thank you for update Stephan! Quote Link to comment Share on other sites More sharing options...
dcmorais Posted December 3, 2015 Report Share Posted December 3, 2015 Hi Stephan, This version will a public release or just for the members of the working group? Thanks, Daniel Quote Link to comment Share on other sites More sharing options...
Stephan Gerth Posted December 4, 2015 Report Share Posted December 4, 2015 Hi Daniel, this will be a _public_ review release. It is already posted here: http://www.accellera.org/downloads/drafts-review/files Quote Link to comment Share on other sites More sharing options...
dave.burgoon Posted June 7, 2016 Report Share Posted June 7, 2016 What is the current status of the UVM-SystemC implementation of the Register Abstraction Layer (RAL), and constrained randomization? The preview release notes indicate that these are not complete. What are the estimated dates for completion of these very important pieces of the UVM? Quote Link to comment Share on other sites More sharing options...
Martin Barnasconi Posted June 10, 2016 Report Share Posted June 10, 2016 This is work-in-progress in the Accellera SystemC Verification Working Group. Too difficult to give any estimations on availability, but I suggest to watch for the announcements around Accellera's DVCon events planned later this year. Accellera member companies are encouraged to join the working groups to help in the creation, testing and debug of these important functionalities. Quote Link to comment Share on other sites More sharing options...
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