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jstahl

uvm-systemc status ?

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The Accellera SystemC Verification Working Group is working hard to make a stable release of the UVM-SystemC library and Language Reference Manual.

Standardization of the API is still ongoing and there are still changes proposed to both library as well as LRM. As soon as things are getting stable, we will consider releasing it. Timing will be defined by the Accellera VWG.

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Hi,

 

there are two packages available to play around,  UVM_ML_OA  from Cadence

 

http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/

 

and UVMC from Mentor,

 

https://verificationacademy.com/verification-methodology-reference/uvmc-2.3.0/docs/html/files/docs/OVERVIEW-txt.html

 

I have tried both and both are quite similar, but I would start with the Mentor  solution ,it is better docmented

Cheers

And have fun!!!

Angel

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Hi Roman,

 

that's true. The part is already removed as we didn't make it until end of last week for various reasons. However, currently we are trying hard to release it by end of this week now.

 

Thank you for update Stephan!

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What is the current status of the UVM-SystemC implementation of the Register Abstraction Layer (RAL), and constrained randomization? The preview release notes indicate that these are not complete. What are the estimated dates for completion of these very important pieces of the UVM?

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This is work-in-progress in the Accellera SystemC Verification Working Group. Too difficult to give any estimations on availability, but I suggest to watch for the announcements around Accellera's DVCon events planned later this year.

Accellera member companies are encouraged to join the working groups to help in the creation, testing and debug of these important functionalities.

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