Jump to content

Array of Ports


Recommended Posts

Hi all,


I have a following design:



I have created a the following Module (in SystemC)


Task Module: (Thread)


This module gets the load of each task, calculate the remaining time, stores the remaining Time in a global "list" called "ActivationTimings" and sends a signal to Timer Module


Timer Module


This Module recieves signal from all the task and choose the minimum value from the "ActivationTiming"and advances the Time through event. And the Task Module is sensitive to the event


The above things happens till the remaining times of all tasks are zero.



Since I need to resue the code, I used Array of ports to communicate. My elaboration would look as follows:




Task *A = new Task("Module Name", .....Task Parameters like speed, load.....);

Task *B = new Task("Module Name"..... T);


sc_signal<bool> connect[2];



A->outputTask(connect[0]);       // outTask is the output port of "Task" Module





Timer T("Timer");


for(int i=0;i<2;i++)



T.InputTimer(connect);    // Using Array of Ports(InputTimer[1]) in Timer Module










The code works perfectly. but, when i am trying to run the simulation for several iterations,




for(int i=0;i<100;i++)






the simulation time gets degraded .


Is array of ports reason for this slowdown?? And If so, Why?










Link to comment
Share on other sites



It seems like sc_vector is exactly what you are looking for.


SystemC LRM IEEE 1666-2011 Section 8.5 sc_vector


It solves the problem that you cannot have an array or std::vector of sc_objects (signals, modules, ...) because they are not default constructible, assignable, copyable.


Another option would be 'the old way': using an array of pointers to sc_signals and instantiating the signals dynamically. But sc_vector is the much better and easier way.




Link to comment
Share on other sites



I just have one more doubt, 



Is it only because array of ports is not default constructable, copyable etc it is resulting in slower performance?



And how sc_vector is more sophesticated than the array of ports in case of simulation speed?



Im sorry for the stupid questions, but I just wanted a clear understanding.






Link to comment
Share on other sites



First of all: We are talking about the model construction and elaboration phase here (instantiating components and binding ports). In general, the simulation phase is the way more performance critical part and not the elaboration.


To your question:

sc_object and all derived classes are not default constructible and copyable. So: it is the port itself and not the array.

If you want to instantiate an array of sc_ports or a std::vector of sc_ports, you need to assign actual values (i.e. sc_port objects) to the individual members of the array or vector. To do so, you would need to copy sc_port objects and this is not allowed.

(In fact, this is somehow possible in C++14, but not in an easy and convenient way.)


Regarding performance:

There is no significant overhead of sc_vector and it is all in the elaboration phase. You will not be able to measure any slow-down. 




Link to comment
Share on other sites

  • 8 months later...

Hi Ralph,


In my design I have also usage of two dimensional ports, and I am declaring that port like sc_vector< sc_in<sc_uint<8> > > IN1;


Now, I have to make a combo process comb_prc (I am doing it as SC_METHOD) which is sensitive to this vector input. But if do like below-




it is giving error :


          no operator "<<" matches these operands                                                                                                                 
            operand types are: sc_core::sc_sensitive <<                                                                                                           


Can you kindly inform how to give sensitivity in this case?


Second problem, I am not able to use .read() also on this vector port. I can see that that there is no read() member function in sc_vector. Hence, how can I use this IN1 in my code?




Link to comment
Share on other sites



There is a difference between sc_vector and comparable things in VHDL.

In VHDL, a signal of a vecctor type is a signal itself.

In SystemC, sc_vector is a container for sc_object elements. I.e., an sc_vector with signals (or ports) as elements is not a signal (or a port). Hence, you cannot be sensitive to the vector and you cannot read from the vector.

Instead, you have to use its elements:

sensitive << IN1[0] << IN1[1] << ...


If you do not want to list all the elements here, you can set up an event_or_list or an event_and_list (IEEE-1666-2011: Sec 5.8). You can easlily fill it in a loop and be sensitive to that list then.


Same for reading:

IN1[0].read() should work.




Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...