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Everything posted by anindya.hazra

  1. Hi, I have three modules A,B and C. I want to integrate these three modules inside TOP module constructor. Now module A has one port sc_out<<sc_uint<2> > out; module B has one port sc_out<<sc_uint<2> > out; module C has one port sc_in<<sc_uint<4> > in; Now inside TOP constructor I have instantiated all these three modules A,B and C. And during connection I am doing following- A_inst->out(out1); B_inst->out(out2); C_inst->in((out2,out1)); out1 and out2 both are sc_signal<sc_uint<2> > ; This is throwing error that concatenation at ports not possible. Is it I am doing something wrong? How to perform these port concatenation directly inside constructor without introducing separate SC_METHOD for that? Regards, Anindya
  2. Hello Roman, Thanks for the information. I have identified the issue. Previously I used like below- sc_module(my_module) { const char *instance_name; sc_has_process(my_module); my_module(sc_module_name name) : sc_module(name) { instance_name = name; } }; Now I have changed my code like below- sc_module(my_module) { const char *instance_name; const char *instance_name_full; sc_has_process(my_module); my_module(sc_module_name name_) : sc_module(name_) { instance_name = name_; instance_name_full = name(); } }; Now I am getting result as- instance_name = only one level hierarchy i.e. the instance of this module only instance_name_full = full hierarchy starting from the instance taken inside sc_main Now I am able to use instance_name_full inside my code as I am getting full hierarchy. Thanks.
  3. Hello Roman, But how to use it inside code? Can you give example for this? Somewhere I had see that sc_module_name also gives instance name. I have used it in my code and it also giving one level hierarchy, but not the full hierarchy starting from top. And I need full hierarchy starting from top i.e. sc_main in my code.
  4. Hi, In my design I have one module instantiated 3 level down the hierarchy from sc_main. And I want to get the full hierarchical path inside that module as I have to generate different files based on the full hierarchy path. To do that I have used- sc_module(my_module) { const char *instance_name; sc_has_process(my_module); my_module(sc_module_name name) : sc_module(name) { instance_name = name; } }; By doing this at "instance_name" I am getting only one level hierarchy, not the full hierarchy. Can you inform me how to get full hierarchy path inside any module?
  5. Hi Ralph, In my design I have also usage of two dimensional ports, and I am declaring that port like sc_vector< sc_in<sc_uint<8> > > IN1; Now, I have to make a combo process comb_prc (I am doing it as SC_METHOD) which is sensitive to this vector input. But if do like below- SC_METHOD(comb_prc); sensitive<<IN1; it is giving error : no operator "<<" matches these operands operand types are: sc_core::sc_sensitive << sc_core::sc_vector<sc_core::sc_in<sc_dt::sc_uint<8>>> sensitive<<iN1; Can you kindly inform how to give sensitivity in this case? Second problem, I am not able to use .read() also on this vector port. I can see that that there is no read() member function in sc_vector. Hence, how can I use this IN1 in my code? Regards, anindya
  6. I am doing systemic & verilog co-simulation using cadence irun tool. When I am using non parameterize constructor and then using NCSC_MODULE_EXPORT it is working fine. But if I use parameterized constructor, then same NCSC_MODULE_EXPORT syntax is not working. Is the NCSC_MODULE_EXPORT different for parameterized constructor?
  7. When systemc design is simulated using cadence irun we can see that modules ports changed to port_0, port_1 etc instead of keeping same port name which are used inside design. How to preserve same port name when simulated using cadence irun?
  8. In Verilog 2001 there is syntax always@(*). It considers all inputs used inside process are taken care in sensitivity list. Is there any equivalent syntax in SystemC?
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