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Test Ends Before All Sequences Are Completed


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I have put together a basic testbench using the 'uvm_easy_labs' example (code included.) The test works fine, except that the sequencer keeps putting out sequences (ok I guess) but the test ends before the last sequence has been verified in the scoreboard. I think there is a way to raise an objection in the scoreboard, but a couple of 'cut-n'-paste' attempts that I tried, did nothing to keep the end of test from cutting off the last sequence generated.

Just for background, the testbench instantiates a VHDL DUT. The VHDL DUT is a CPLD that takes in an 8 bit serial (bit banged) command using cmd_dat and cmd_clk. The leading bit indicates one of two command types, a DISPLAY command or an FET command. The display command sends 4 bits of output to a display port with write and e logic output from the CPLD, where as an FET command sets one or more output bits on a 7 bit mosfet port.

The makefile has a commented entry to run the test in the gui (questasim) mode or in the typical text output only mode. I created the gui makefile entry to be able to look at the waves display (it was a quick way of seeing what was going on without writing more extensive 'monitor (receiver) code to textually describe the CPLD code. As a second question, it would be nice to figure out how (where) to extend the uvm_info class to put the timescale (us, ns, ps etc) on the end of the time string (that way, if in gui mode, you can just double-click on a time entry and the cursor will move to that location in the waves window.)

I think it is fine to keep generating sequences forever based on some criteria, but there should be a method to gracefully end the test with all 'generated' sequences accounted for.

Edited by mrmikehicks
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While waiting for some advice, I have added a phase.phase_done.set_drain_time(this, 2500ns); to the run_phase of the test class:

class rand_transfer extends dut_test_base;

`uvm_component_utils(rand_transfer)

function new(string name = "rand_transfer", uvm_component parent = null);

super.new(name);

endfunction

task run_phase(uvm_phase phase);

rand_order_seq seq = rand_order_seq::type_id::create("seq");

phase.phase_done.set_drain_time(this, 2500ns);

phase.raise_objection(this, "Starting rand_transfer test");

repeat(3) begin // will run 12 tests

seq.start(m_agent.m_sequencer);

end

phase.drop_objection(this, "Finishing rand_transfer test");

endtask: run_phase

endclass: rand_transfer

I'm not happy with this fix, (although in this case it works.) I think this is really kludgy and there must be a better handshake method to do this kind of thing.

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Well, I know it's about 2500 ns, since that's what works to leave enough time for the scoreboard to process the command, but what I would really like is the correct syntax to add the 'raise' and 'lower' objections to the scoreboard (The scoreboard has no task as written now, and I wasn't sure how to add an objection that would wait until the sequencer is finished and then process the last seq in the scoreboard)

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