uvm_reg_fifo with multiple interfaces/address maps

[johannes.walter]

hey!

i have got a problem with a fifo register in UVM. there are two interfaces. one can write to the fifo register and the other can read from it.

at first i tried to solve this by using a virtual sequencer and choose the right sequencer for every sequence. but UVM just ignores this and uses the sequencer associated with the register model's address map.

so i tried to implement two address maps - one for each interface - and add all the registers to both maps. but on adding the fifo registers to both maps i get the following errors:

# UVM_ERROR /home/walterjo/uvm-1.1/src/reg/uvm_reg_field.svh(938) @ 0: reporter [RegModel] Shared register 'reg_model.global_processing_call_reg' containing field 'value' is not shared in map 'reg_model.spi_map'
# UVM_ERROR /home/walterjo/uvm-1.1/src/reg/uvm_reg_field.svh(938) @ 0: reporter [RegModel] Shared register 'reg_model.global_processing_status_reg' containing field 'value' is not shared in map 'reg_model.spi_map'
# UVM_ERROR /home/walterjo/uvm-1.1/src/reg/uvm_reg_field.svh(938) @ 0: reporter [RegModel] Shared register 'reg_model.global_processing_call_reg' containing field 'value' is not shared in map 'reg_model.porc_map'
# UVM_ERROR /home/walterjo/uvm-1.1/src/reg/uvm_reg_field.svh(938) @ 0: reporter [RegModel] Shared register 'reg_model.global_processing_status_reg' containing field 'value' is not shared in map 'reg_model.porc_map'
# UVM_FATAL @ 0: reporter [BUILDERR] stopping due to build errors

has anyone an idea how to deal with multiple interfaces on fifo registers correctly?

any help would be highly appreciated!

regards,

johannes