Jump to content

uvm_reg_access_seq can't test registers with RO fields. Why?


Recommended Posts

So, why does the uvm_reg_access_seq skip registers that have RO fields? I would think that accessing via back door using read() and write() would properly predict and set values according the access policies of each field. Indeed, when I comment out the code that skips the RO registers, the sequence is able to operate on registers with RO fields without errors.

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...