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uvm_reg_access_seq can't test registers with RO fields. Why?

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So, why does the uvm_reg_access_seq skip registers that have RO fields? I would think that accessing via back door using read() and write() would properly predict and set values according the access policies of each field. Indeed, when I comment out the code that skips the RO registers, the sequence is able to operate on registers with RO fields without errors.

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