UVM Register Package - uvm_reg_bus_op

[badgerbot]

Hi,

I'm using the uvm_reg_pkg in an OVM environment. I'm using AXI as the register interface bus. I'm using the (from uvm 1.1 user guide) "Register Sequence Running on a Layered Register Sequencer".

I need protection and response information in the uvm_reg_bus_op but since it's a struct i cannot extend it. I tried creating a new struct (uvm_reg_bus_prot_op) but it gave an error since the overridden reg2bus fucntion expected the original type.

Does anyone know how to get this extra information into a register transaction without having to re-write a lot of code.

thanks

[janick]

The bus_op is created by the register layer. And because the register layer has no knowledge of the concept of your bus-specific protection and response, there is nowhere this information can be annotated on this data type. It can be added to the bus-specific uvm_sequence_item that the bus_op gets translated to, but where are the protection/response values coming from? They could come from the resource database and your conversion function could extract the values to be used from it. It could be randomly generated. It could also be specified in each read/write operation using the "extension" argument, the value of which can be obtain by using the get_item() method from within your reg2bus() conversion function.

[badgerbot]

Hi Janick,

Thanks a lot for the feedback. Using the "extension" argument seems like the preferred choice for me.

I extended a new class and added the protection control bit (i've omitted the new function etc for clarity throughout this message):

typedef enum bit {SECURE, NONSECURE} prot_t;

class uvm_reg_item_prot extends uvm_reg_item

prot_t prot;

endclass

In my sequence i assign the prot to the desired value. However since the type is "ovm_object extension" and the return type from get_item is uvm_reg_item, i got a type incompatibility. I need to cast inside the reg_2bus function:

ovm_sequence_item reg_item;

uvm_reg_item_prot ste_rw;

reg_item = get_item(); //get the "extension" variable from the write_reg arguments to get the prot information

$cast(ste_rw, reg_item);

I can't yet verify if this works since i have trouble starting my register sequence which i'll now describe.

I am using a layer sequence approach. I have a virtual sequencer on which i run a virtual sequence to start many different sequences on different VIP's one of which is the register sequencer.

In the virtual sequencer i instance the register sequencer:

ovm_sequencer#(uvm_reg_item) v_reg_seqr;

This is connected in my env to the register sequencer:

function void build();

reg_seqr = uvm_sequencer#(uvm_reg_item)::type_id::create("reg_seqr",this);

endfunction

function void connect();

regmodel.default_map.set_sequencer(reg_seqr,null);

reg2axi_seq.reg_seqr = reg_seqr;

v_sqr.v_reg_seqr = reg_seqr;

endfunction

and finally in my virtual sequence i start the sequence on the sequencer:

write_one_reg_seq w_one_reg_seq;

task body();

w_one_reg_seq = write_one_reg_seq::type_id::create("w_one_reg_seq");

w_one_reg_seq.start(v_sqr.v_reg_seqr);

endtask

Note : the w_one_reg_seq calls the write_reg function and is derived from uvm_reg_sequence i.e:

class write_one_reg_seq extends uvm_reg_sequence #(uvm_sequence #(axi_rw_t));

I get an error of : Wait_for_grant called on sequencer with no driver connected

Am i connecting the v_sqr to the correct register sequencer? If i am, how do i initiate a register sequence on it?

thanks

[janick]

You don't extend the uvm_reg_item, you create a uvm_object extension that contains your additional information and pass it as the value of the 'extension' argument. You can then recover it from the uvm_reg_item inside the reg2bus() method.

class my_info extends uvm_object;

prot_t prot;

endclass

...

my_info inf = new();

inf.prot = SECURE;

regmodel.reg.read(status, rdat, .extension(inf));

...

function uvm_sequence_item reg2bus(...);

uvm_reg_item item = get_item();

$cast(inf, item.extension);

...

endfunction