backdoor access for RC (Clear on read) register

[ramkodanda]

Hi,

I am using a register model with one of the register is RC accessing policy.

The rc register content is not becoming zero with backdoor read.

Related code is as follows:

sequence:

model.DATA_RC.read(status,datar,.path(UVM_BACKDOOR),.parent(this));

regmodel.sv:

The configuration of rc register is as followes:

class dut_rc_DATA extends uvm_reg;

- - - -

value.configure(this,32,0,"RC",1,32'h99999999,1,0,1);

- - - -

endclass

and in the reg_block,

class dut_regmodel extends uvm_reg_block;

- - - -

DATA_RC.configure(this,null,"DATA_RC");

- - - -

endclass

With FRONTDOOR access rc register contents are becoming zero.

[janick]

This bug has already been reported: http://www.eda.org/svdb/view.php?id=3631