johannes.walter Posted July 26, 2011 Report Share Posted July 26, 2011 (edited) Hey! I'm about to implement some register tests. So first of all I wanted to run all the UVM built-in test sequences. But when I run the uvm_reg_access_seq I get the following error in QuestaSim: ** Fatal: (SIGSEGV) Bad handle or reference. Time: 1531 ns Iteration: 0 Process: /uvm_pkg::uvm_sequence_base::start/#FORK#285_2a96f3307 File: /opt/questasim_10.0b/questasim/verilog_src/uvm-1.0p1/src/dpi/uvm_hdl.svh Fatal error in Module uvm_pkg at /opt/questasim_10.0b/questasim/verilog_src/uvm-1.0p1/src/dpi/uvm_hdl.svh line 121 I had a look at uvm_hdl.svh, line 121. It imports a C function from uvm_hdl.c which I cannot debug. Has anyone an idea how I could fix this? Regards, Johannes Edited July 26, 2011 by johannes.walter Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.