johannes.walter Posted July 26, 2011 Report Posted July 26, 2011 (edited) Hey! I'm about to implement some register tests. So first of all I wanted to run all the UVM built-in test sequences. But when I run the uvm_reg_access_seq I get the following error in QuestaSim: ** Fatal: (SIGSEGV) Bad handle or reference. Time: 1531 ns Iteration: 0 Process: /uvm_pkg::uvm_sequence_base::start/#FORK#285_2a96f3307 File: /opt/questasim_10.0b/questasim/verilog_src/uvm-1.0p1/src/dpi/uvm_hdl.svh Fatal error in Module uvm_pkg at /opt/questasim_10.0b/questasim/verilog_src/uvm-1.0p1/src/dpi/uvm_hdl.svh line 121 I had a look at uvm_hdl.svh, line 121. It imports a C function from uvm_hdl.c which I cannot debug. Has anyone an idea how I could fix this? Regards, Johannes Edited July 26, 2011 by johannes.walter Quote
johannes.walter Posted July 26, 2011 Author Report Posted July 26, 2011 Okay. I did some more debugging. I forgot to mention that my DUT is written in VHDL. So I would like to access some VHDL std_ulogics and std_ulogic_vectors using the UVM backdoor. So here is what I found out: The function "uvm_hdl_get_vlog" in uvm_hdl.c works well when I am trying to access a std_ulogic register. But the segmentation fault occurs when I try to get access to the value auf a std_ulogic_vector register. Seems like the DPI/VPI extension cannot handle VHDL std_ulogic_vectors. Has anyone had such a problem before? Regards, Johannes Quote
johannes.walter Posted July 26, 2011 Author Report Posted July 26, 2011 Hey! The segmentation fault has gone away. I had to add the range of the std_ulogic_vector to the HDL path. adc_conf_reg.add_hdl_path('{ '{"sfr_adc_conf_reg_s[6:0]", -1, -1} }); ... did the trick.But now I have got another error. The uvm_hdl.c function tries to access each bit of the vector indiviually. But QuestaSim cannot find these paths. Here is the error: # UVM_ERROR: get: unable to locate hdl path top.dut.sfr_adc_conf_reg_s[0] # Either the name is incorrect, or you may not have PLI/ACC visibility to that name What am I doing wrong? I also compiled every source file with +acc=rnb. Regards, Johannes Quote
johannes.walter Posted July 26, 2011 Author Report Posted July 26, 2011 (edited) This problem disappeared during development ... but now there is another one with accessing std_ulogic_vectors using the DPI/VPI. I will open another thread for this: http://www.uvmworld.org/forums/showthread.php?327-Valid-HDL-path-using-DPI-VPI-to-access-std_ulogic_vectors Regards Edited July 27, 2011 by johannes.walter Quote
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