uvm_reg_mem_hdl_paths_seq

[paul]

hello,

I have some issues when I run uvm_reg_mem_hdl_paths_seq. I have two similar block containing the same registers, my hdl_path of blocks in my regmodel is declared as follow:

default_map = create_map("default_map", 'h0, 16, UVM_BIG_ENDIAN, 0);

default_map.add_submap(VW_OUTBOUND1.default_map, 'h00000);

VW_OUTBOUND1.clear_hdl_path();

VW_OUTBOUND1.add_hdl_path("u_OUT1[0]");

and

default_map = create_map("default_map", 'h0, 16, UVM_BIG_ENDIAN, 0);

default_map.add_submap(VW_OUTBOUND1.default_map, 'h10000);

VW_OUTBOUND1.clear_hdl_path();

VW_OUTBOUND1.add_hdl_path("u_OUT1[1]");

but I receive a fatal error telling me that the reference is wrong (error at line 121 of uvm_hdl.svh). This error happens only when this sequence is running.

Do anyone have some explanations?

thank,

paul

[janick]

Where do the the "[0]" and "[1]" in the HDL path come from? You can't have module arrays.

Are these two instances created using a generate statement?

can you show the HDL code in your module where u_OUT* are instantiated?