yyn Posted July 3, 2011 Report Share Posted July 3, 2011 Hello, I have a question for analysis port connection. A UVC monitor that I use provides anaylsis port as followings (I provided this monitor from vendor). ************************************************** uvm_analysis_port #(uvm_sequence_item) monitor_item_done; ************************************************** I'd like to connect this port to "bus_in" of "uvm_reg_predictor" in my testbench. "bus_in" is a port that is provided from UVM library. ***************************************************** uvm_anaylsis_imp #(BUSTYPE, uvm_reg_dredictor #(BUSTYPE)) bus_in; ***************************************************** In my testbench code, I connected as followings, but this does not work in simulator. ********************************************************* if_env.master.monitor.monitor_item_done.connect(bus2reg_predictor.bus_in); ********************************************************* "axi2reg_predictor" is the handler name of "uvm_reg_predictor". How can I connect "bus_in" with "monitor_item_done"? Thanks & Regards, Quote Link to comment Share on other sites More sharing options...
uwes Posted July 4, 2011 Report Share Posted July 4, 2011 hi, can you share more of what "is not working"?. is it not compiling?, not giving the expected results? not seeing any traffic? /uwe Quote Link to comment Share on other sites More sharing options...
yyn Posted July 4, 2011 Author Report Share Posted July 4, 2011 Hi uwes, Error is compilation error of IES. Actually I already asked to Cadence support center, and I am still waiting for reply. But this is very urgent to me. Error message is "E, TYCMPAT: formal and actual do not have assignment compatible data types (expecting datatype compatible with 'specialization of class uvm_port_base' but found 'specialization of class uvm_analysis_imp' instead). I hope to obtain solution anywhere quickly. Thanks for your interest in advance. Quote Link to comment Share on other sites More sharing options...
uwes Posted July 5, 2011 Report Share Posted July 5, 2011 hi, you cant directly connect a port of "uvm_sequence_item" to a receiving end of expecting "BUSTYPE". (i assume BUSTYPE is NOT uvm_sequence_item) >Is there any way to make the two compatible? there are a few ways: 1. make the port monitor_item_done a port sending BUSTYPE items 2. make the repredictor receiving uvm_sequence_items and $cast the generic items inside the predictor to your BUSTYPE 3. create a proxy component with one tlm in-port of type uvm_sequence_item and one out port of BUSTYPE and simply cast inside the write function to the BUSTYPE and send the $casted element further. you might want to look at http://uvm.git.sourceforge.net/git/gitweb.cgi?p=uvm/uvm;a=tree;f=tests/70regs/40addons/02_simple_seq_bkdr_ftdr;h=e44900ee1ac6d615a8079c3ae3b85ba79b0fb0f0;hb=master the relevant code parts are: class transaction extends uvm_sequence_item; // predictor def and analysis port must have same types uvm_reg_predictor#(transaction) predictor; uvm_analysis_port#(transaction) item_collected_port; // connect uenv.drv.item_collected_port.connect(predictor.bus_in); Quote Link to comment Share on other sites More sharing options...
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