Experimenting with phases and sequences

[girodias]

I'm not sure what to make of the following situation:

I've layered two sequences and set up the upper-layer sequence to start as a default sequence in several phases: post_reset_phase, pre_main_phase, main_phase. The bottom layer sequence is manually started by my test in pre_main_phase. As the title says, this came about as I was experimenting with UVM.

Each sequence has its own sequencer. Effectively, the items from the upper-layer sequence are not intended to be used before the pre_main_phase; they are simply "available" before.

As expected, the upper-layer sequence starts in all of the above phases. The bottom layer sequences starts correctly in pre_main_phase but gets stuck trying to retrieve items from the upper layer sequencer (the peek statement in get_next_item).

I briefly tried tracing the execution of the UVM code and it appears that the request_id from the upper_layer sequence that got started in post_reset_phase is the one that gets marked as complete by the sequencer arbitration process during pre_main_phase. I'm assuming that the sequence request id for the pre_main_phase is the one that is expected and hence that is gating things, but admittedly I don't have the full picture in mind yet.

Should the left-over sequence request ID from the post_reset_phase have been cleared when that phase ended? Or is this expected behaviour? Is the user responsible for ensuring that all sequences are properly terminated before the next phase begins?

Of course, everything works fine if I do not start the upper-layer sequence before pre_main_phase.

[girodias]

Here's an example of what I tried explaining above:

program test;

import uvm_pkg::*;
`include "uvm_macros.svh"

class my_item extends uvm_sequence_item;

  rand integer data;

  `uvm_object_utils_begin(my_item)
    `uvm_field_int(data, UVM_ALL_ON + UVM_DEC)
  `uvm_object_utils_end

endclass

class my_seq extends uvm_sequence #(my_item);

  `uvm_object_utils(my_seq)

  function new(string name = "");
    super.new(name);
  endfunction : new

  task body();
    forever begin
      `uvm_do(req)
    end
  endtask : body

endclass : my_seq

class my_test extends uvm_test;

  `uvm_component_utils(my_test)

  uvm_sequencer #(my_item) seqr;

  function new(string name = "my_test", uvm_component parent);
    super.new(name, parent);
  endfunction : new

  function void build_phase(uvm_phase phase);
    seqr = new("seqr", this);
    uvm_resource_db #(uvm_object_wrapper)::set({get_full_name(), ".seqr.pre_main_phase"}, "default_sequence", my_seq::type_id::get(), this );
    uvm_resource_db #(uvm_object_wrapper)::set({get_full_name(), ".seqr.main_phase"}, "default_sequence", my_seq::type_id::get(), this );
  endfunction : build_phase

  task main_phase(uvm_phase phase);
    my_item item;
    phase.raise_objection(this);
    repeat (10) begin
      seqr.get_next_item(item);
      `uvm_info(get_name(), $psprintf("%0d", item.data), UVM_NONE);
      seqr.item_done();
    end
    phase.drop_objection(this);
  endtask : main_phase

endclass : my_test

initial run_test("my_test");

endprogram : test

If I don't specify a default sequence for the pre_main phase, everything works fine. If I do specify the default sequence for the pre_main phase, the simulation times out because the call to get_next_item never returns.

Is this to be expected?

I know there are other ways to have a sequence span several phases, I'm just trying to understand how this all works.

Edited June 8, 2011 by girodias