Layered Sequencers

[jsree]

Hi

as per Uvm_users_guide_1.0 section 7.4.2.5 /7.4.2.6. Tried to create Layered Sequencer but due to my lack of understanding on config_db the example failed. ( I will post the error message regarding this later)

Using similar concept, created layer using virtual sequencer.

we have two working UVC with its own Sequences.

1. working UVC - simple (lower UVC)

2. working UVC - pkt (Upper UVC)

the pkt UVC is sequence are generated by testcase and translator will convert pkt sequence to simple sequence and use Lower UVC sequencer and drive TO DUT

1. Create a virtual Sequencer

class layer_virtual_sequencer extends uvm_sequencer;

        simple_pkg::simple_sequencer simple_tx_sequr;
        pkt_sequencer pkt_sequencer;
    ...

...

endclass : layer_virtual_sequencer

2. Created virtual Sequence

class layer_2nd_vseq extends layer_base_vseq;


        simple_pkg::simple_tx_simple_trans_seq tx_trans_seq;

        virtual task body();
        int i;
        pkt_lib::pkt_lib t;        fork
                fork
                begin
                        i = 1;
                        forever begin
                                p_sequencer.pkt_sequencer.get_next_item(t);
                                //copy the stuff from t to 
                                 `uvm_do_on_with(tx_trans_seq, p_sequencer.simple_tx_sequr, {s_data == cnt;})                                        
                                  p_sequencer.pkt_sequencer.item_done();
                                i++;
                        end
                end
                join_none
                begin

                                `uvm_do_on(my_seq_lib,p_sequencer.pkt_sequencer)
                end

        join

        endtask

endclass : layer_2nd_vseq

3. create a testcase use the above virtual sequence to virtual sequencer

class simple_test1 extends uvm_test;

        layer_env tb_env;
        pkt_sequencer pkt_sequencer;
        `uvm_component_utils(simple_test1)

         function new(string name, uvm_component parent=null);
                super.new(name,parent);
        endfunction

        virtual function void build_phase(uvm_phase phase);

                super.build_phase(phase);

        uvm_config_db#(uvm_object_wrapper)::set(this, "tb_env.virtual_sequencer.run_phase",
          "default_sequence", layer_2nd_vseq::type_id::get());

        tb_env = csco_layer_env::type_id::create("tb_env",this);
        pkt_sequencer = pkt_sequencer::type_id::create("pkt_sequencer",this);

  endfunction : build_phase




        function void connect_phase(uvm_phase phase);
                super.connect_phase(phase);
                tb_env.virtual_sequencer.pkt_sequencer = pkt_sequencer;
                itb_env.virtual_sequencer.simple_tx_sequr = tb_env.simple0.simple_tx_agent.sequencer;

        endfunction



endclass

Created sequence library out of pkt Sequence and that Sequence-lib is default sequence for virtual sequencer's pkt_sequencer using config_db

in the connect phase virtual sequencers upper/lower is connected properly

in the virtual sequence the task body does the translation.

Please let me know any issue with this approach of Layering.

thanks in Advance

Jay