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How to add new enumerated type to define user register coverage?


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Hello,

UVM-1.p01 provides a few kinds of register coverage. For this, enumerated type is defined as followings.

== In "uvm_reg_model.svh" ===

typedef enum uvm_reg_cvr_t {

UVM_NO_COVERAGE = 'h0000,

UVM_CVR_REG_BITS = 'h0001,

UVM_CVR_ADDR_MAP = 'h0002,

UVM_CVR_FIELD_VALS = 'h0004,

UVM_CVR_ALL = -1

} uvm_coverage_model_e;

=====================

How to add new type "UVM_CVR_REG_KIND"?

I'd like to add only new type or to override through redefining in any file of my testbench environment.

I do not want to edit UVM library.

How can I override enumerated type which is already defined somewhere?

Thanks,

yyn

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SystemVerilog provides no way to override or extend enums. You could create you're own type which uses the UVM defined values for the overlapping fields. Or if strict enum typing is not required you could just define your extra values and use an int to mix values from both types.

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Dear jadec,

Thanks for your answer.

If possible, could you give an example code of your answer?

Is there good example using built-in functions such as get_coverage() and include_coverage() for customized type "UVM_CVR_REG_KIND" ?

I'd like to contorl coverage on or off as below after adding my type :

uvm_reg::include_coverage("*", UVM_CVR_REG_KIND + UVM_CVR_FIELD_VALS);

Thanks a lot.

YYN

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typedef enum uvm_reg_cvr_t {

MY_UVM_CVR_REG_KIND = 'h0100

} my_uvm_coverage_model_e;

uvm_reg::include_coverage("*", uvm_coverage_model_e'(MY_UVM_CVR_REG_KIND + UVM_CVR_FIELD_VALS));

This assumes that the model knows what to do with the user-defined value. It looks like internally UVM stores this in an "int".

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