jsree Posted May 16, 2011 Report Share Posted May 16, 2011 Hi I coded sequence lib as follows class simple_seq_lib extends uvm_sequence_library#(my_trans); `uvm_object_utils(simple_seq_lib) `uvm_sequence_library_utils(simple_seq_lib) `uvm_add_to_seq_lib(nomacro_seq, simple_seq_lib); `uvm_add_to_seq_lib(directed_seq, simple_seq_lib); `uvm_add_to_seq_lib(super_seq, simple_seq_lib); // Weights only apply when using UVM_SEQ_LIB_RAND mode constraint select_rand_dist { select_rand dist { 0 := 70, // nomacro_seq 1 := 20, // directed_seq 2 := 10 // super_seq }; } function new(string name=""); super.new(name); init_sequence_library(); endfunction endclass in the testcase coded as follows class third_seq_test extends demo_base_test; typedef uvm_config_db#(uvm_object_wrapper) phase_cfg; pkt_lib::simple_seq_lib my_seq_lib; `uvm_component_utils(third_seq_test) function new(string name = "third_seq_test", uvm_component parent); super.new(name,parent); endfunction : new virtual function void build_phase(uvm_phase phase); my_seq_lib = new("my_seq_lib"); void'(my_seq_lib.randomize()); uvm_config_db#(uvm_sequence_base)::set(this, "demo_tb0.tm.simple_tx_agent.sequencer.main_phase", "default_sequence", my_seq_lib); // Create the testbench super.build_phase(phase); endfunction endclass : third_seq_test in the testcase I like to constraint some field in nomacro_seq (sequence item 0), Please let me know how to code the same Thanks in Advance Jay Quote Link to comment Share on other sites More sharing options...
jadec Posted May 17, 2011 Report Share Posted May 17, 2011 One way is to subclass that sequence (and add the constraint in the subclass) then use the factory to replace it. Quote Link to comment Share on other sites More sharing options...
jsree Posted May 17, 2011 Author Report Share Posted May 17, 2011 Hi Jadec Still it is not very clear, could you please post sample code. Thanks Jay Quote Link to comment Share on other sites More sharing options...
jadec Posted May 17, 2011 Report Share Posted May 17, 2011 From examples/simple/factory/test.sv: class mypacket extends packet; constraint ct10 { addr >= 0 && addr <= 10; } //Use the macro in a class to implement factory registration along with other //utilities (create, get_type_name). `uvm_object_utils(mypacket) endclass initial begin packet::type_id::set_type_override(mypacket::get_type()); You can do the same thing for your sequence type. Quote Link to comment Share on other sites More sharing options...
jsree Posted May 17, 2011 Author Report Share Posted May 17, 2011 HI Jadec Thanks. Let me review this examples more and figure it out it helps me to constaint the sequce inside a existing sequence lib. Jay Quote Link to comment Share on other sites More sharing options...
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