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Port Encapsulation


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Hello, I am working on a model where I am attempting to encapsulate ports. The following code groups sc_in/sc_out ports together based on what bus they belong to. Then I can use arrays to declare the desired number of each type of bus. 


template <typename T_ADDR, typename T_DATA>

class ReadBus {
sc_in<T_ADDR>   address;
sc_out<T_DATA> data;
template <typename T_ADDR, typename T_DATA>
class WriteBus {
sc_in<T_ADDR>  address;
sc_in<bool>         wen;
sc_in<T_DATA>  data;
class someblock<T_ADDR, T_DATA, n_rp, n_wp> : public sc_module {
sc_in_clk clock;
ReadBus<T_ADDR, T_DATA> read_ports[n_rp];
WriteBus<T_ADDR, T_DATA> write_ports[n_wp];

The model compiles and simulates fine but I am wondering if this is synthesizable?


It isn't clear to me from looking at the public draft of the synthesizable subset if this is supported. I don't have access to any vendor tools at the moment or I'd try it directly...




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