Use of Vera in a UVM environment?

[srinivaspudu]

Is there a way to use a Vera models or Vera tasks inside a UVM env in VCS?

Do we have to code everything again in systemverilog?

[chrisspear]

VCS has supported SV calling Vera and Vera calling SV for a long time. Likewise, Vera classes can be instantiated in SV, and even extended from one language to another.The two languages are close enough that one compiler can handle both languages. So keep your tried and true Vera code and use it in your UVM testbench.

Of course you need to plan how to merge the test phases in your Vera models with UVM, but the new methodology has constructs specifically designed for this.

Chris Spear

Synopsys