Jump to content

Use of Vera in a UVM environment?

Recommended Posts

VCS has supported SV calling Vera and Vera calling SV for a long time. Likewise, Vera classes can be instantiated in SV, and even extended from one language to another.The two languages are close enough that one compiler can handle both languages. So keep your tried and true Vera code and use it in your UVM testbench.

Of course you need to plan how to merge the test phases in your Vera models with UVM, but the new methodology has constructs specifically designed for this.

Chris Spear


Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...