olofk Posted February 17, 2015 Report Share Posted February 17, 2015 Hi,I finally started to explore IP-XACT with the intention of creatingbus definitions and interface models for most of the cores we use inthe OpenRISC ecosystem. During my brief encounter I have come across afew practical issues where I'm interested in guidance on bestpractices.1. Is there a publicly available central registry for common thingslike bus definitions? It feels like half of the idea of the standardis lost if everyone is pusing their own SPI, I2C, SDRAM buses and soon.2. How do I treat variants of a bus? The most common bus we use is theWishbone bus, and there are a few variants of it. It has seen at leastthee revisions (called b2, b3 and b3) with signals added in eachrevision, and it also comes in different widths with 32 and 8 bitsbeing the most common. It seems to me like I would need to create 3x2= 6 different combinations to cater this. I'm also not sure what wouldbe the preferred naming scheme for this. One way is to create sixdifferent versions (e.g. b3.8, b3.32, b4.8, b4.32... etc). Another wayis to give different VLNV names to the different data widthcombinations (e.g. wishbone32 with versions b2, b3, b4 and wishbone8with versions b2, b3,b4). I'm basically looking for best practices forthis.3. Are the bus definitions parametrizable? I'm using an Open sourceIP-XACT tool called Kactus2, and it doesn't allow me to set paramtersfor buses, but I haven't figured out if this is a tool limitation orif the standard prevents configuration. I have come across this issuefor DRAM interfaces where I would like to vary address width, datawidth and so on to avoid having a myriad of similar buses.Best Regards,Olof Kindgren Quote Link to comment Share on other sites More sharing options...
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