Memory initialisation

[veljkom]

Hi All,

I've been trying to have a memory module initialised in reset state.

 

I've got something like this:

template< class address_bus, class data_bus, unsigned int depth>
SC_MODULE(sp_memory){
sc_in<bool> clk;
sc_in<bool> nrst;

sc_in<address_bus> addr_i;
sc_in<data_bus> data_i;
sc_in<bool> wr_i;
..
   ...
   void sp_mem_process();
   data_bus mem[depth]; // for instance in this case data_bus=sc_uint<32>
   ..
   SC_CTOR {
   ..
   SC_CTHREAD(sp_mem_process, clk.pos());
   reset_signal_is(nrst,false);
   ..
   }
};

So, after several trials I ended up with the following best case,which is OK for simulation but still could not be synthesised.

template< class mem_word, unsigned int depth, const char * mem_init_file>
SC_MODULE(sp_memory){
..
};

This means I give content of a init file to each memory module instance, after which the array mem is initialised with the content of the file in a loop in reset state of the process sp_mem_process().

This is not synthesis-able in the tool I'm using and I believe it's not up to the tool?

 

So, I want to have a synthesis-able memory initialised from a init_file in pre-reset state. What is your experience on this?

 

 

I know that the brute force solution is that the memory is initialised externally, by writing to it as soon as it leaves reset state, but this is not compliant with the HW behaviour that normally can be found in, for instance, FPGA block RAM.

 

Thanks a lot!

Veljko

 

 

 

 

 

 

 

[apfitch]

I don't know about SystemC synthesis tools, but generally for VHDL/Verilog synthesis tools you'd typically use the place and route tools together with component instantiation to initialize a memory. But the answer is tool specific, so you'll have to read the manual of the tool you're using, or contact the vendor,

 

regards

Alan