praneeth87 Posted May 28, 2014 Report Share Posted May 28, 2014 Hi,I have a doubt related to UVM 's RAL with compared to OVM's RGM. The OVM's RGM seems to have only two sets of registers i.e., the actual ones belonging to DUT and the other belonging to the register model(testbench side regs to mimic duts regs). But the UVM's RAL has three sets namely 1) DUT's regs as usual and 2)Mirror registers 3)Desired value registers, the 2) and 3) are part of the testbench i.e., register model side. Why is this kind of implementation has been adopted in UVM RAL where as we could accomplish our tasks with the 2 sets as is in RGM. Can any one please enlighten me regarding the advantages or usecases related to this?Thanks In advance. Quote Link to comment Share on other sites More sharing options...
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