mbm_30 Posted May 12, 2014 Report Share Posted May 12, 2014 Hi, I am using UVM heartbeat in my testbench and defining UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, so the run time phase will be of type 'uvm_callbacks_objection' instead of 'uvm_objection'. In order to do some end of sim checks, i am waiting for 'phase.wait_for_state(UVM_PHASE_READY_TO_END, UVM_EQ);' Looks like the phase's state is not changing to 'UVM_PHASE_DONE', it is still 'UVM_PHASE_EXECUTING'. The total objection count is 0. During this time, heartbeat event is getting triggered and test is ending with a fatal msg, which is not expected. Configured Hearbeat mode = UVM_ANY_ACTIVE. Heartbeat_window = 100000;; Snippet from log: The total objection count is 0 Heartbeat : Triggering an heart beat event at T= 190624 ns .... .... The total objection count is 0 .... .... Heartbeat : Triggering an heart beat event at T= 381249 ns The total objection count is 0 The total objection count is 0 UVM_FATAL @ 381249046875: env [HBFAIL] Did not recieve an update of run on any component since last event trigger at time 190624047000. The list of registered components is: Am i missing some thing ? Can some one please help in debugging this. Thanks. Quote Link to comment Share on other sites More sharing options...
mbm_30 Posted May 20, 2014 Author Report Share Posted May 20, 2014 Can anyone please help in this. Thanks Quote Link to comment Share on other sites More sharing options...
mpettigr1 Posted June 13, 2014 Report Share Posted June 13, 2014 Have you taken a look at the white paper from synapse-da entitled "UVM Heartbeat" http://www.synapse-da.com/Resource-Center/Whitepapers It does a fairly deep dive into the topic. Quote Link to comment Share on other sites More sharing options...
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