UVM_REG and multiple reset

[yyn]

Hi,

 

I am testing multiple reset.

 

My testbench is based on UVM_REG and I am using "write()" API to write registers.

If reset is asserted when write() is executed, the next warning occurs.

 

UVM_WARNING (UVM/FLD/SET/BSY) Setting the value of field "xxx" while containing register "yyy" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

 

As I debugged, the error is caused by "m_is_busy" variable of uvm_reg.svh.

While write() is executed "m_is_busy" is set to 1 and set to 0.

 

When reset is asserted, user scenario kills write() operation and reset all registers as calling reg_block.reset().

If reg_block.reset() is executed, mirrored value seems to be reset but desired value does not.

 

And also, if reset is asserted between the time that "m_is_busy" is set to 1 and the time that "m_is_busy" is set to 0, "m_is_busy" remains "1". The same register is accessed later again, the above warning occurs.

 

I think this warning is no effect for simulation result. But I want to clear this warning.

Should user control UVM internal variable such as m_is_busy?

When reset is asserted, what is right that which value the desired value of field has?

How can I clear this warning?

 

Thanks & Regards,

yyn