creating register model ?

[mohitnegi]

Hello All ,

 

Well i have to create register model from the defined spec ...

where to start from ...??? no register modelling library required at this stage ..

 

 

[dakupoto]

Hello All ,

 

Well i have to create register model from the defined spec ...

where to start from ...??? no register modelling library required at this stage ..

Hello Sir,

Your question is vague. A simple and efficient register model is

already there in SystemC -- bit vector. Is there any specific register

type you wish to implement -- serial-in parallel-out or vice-versa ?

[mohitnegi]

Hello Sir,

Your question is vague. A simple and efficient register model is

already there in SystemC -- bit vector. Is there any specific register

type you wish to implement -- serial-in parallel-out or vice-versa ?

well i mean i have memory mapped configuration register which are configured by CPU ...

I order to implement them in systemC model i wish to know how should i appoarch registers are

RO,WO ,RW etc ..

[karandeep963]

Well you then need to create masks for the same like READ_MASK , WRITE_MASK and set the values as per the register characteristics number of bits.

So the write data at register would be WRITE_DATA & WRITE_MASK , while the read data would READ_VALUE & READ_MASK .

 

And for mimicing RO, WO etc , you can create two api read_reg and write_reg which linked the pointer to register value. So you can implement accordingly , as an example of RO.

 

read_reg

CASE(REG)

REG1: RO only register

read_value = reg_name -> read_value;

 

For write:

write_reg 

CASE(REG)

REG1: RO only register

cout << "Invalid Write a RO register" << endl;

 

There is no recommended approach as much I am aware, people architects it in their own way.

 

Regards,

Karandeep

[dakupoto]

well i mean i have memory mapped configuration register which are configured by CPU ...

I order to implement them in systemC model i wish to know how should i appoarch registers are

RO,WO ,RW etc ..

Hello Sir,

Most likely, these conditions have to be imposed artificaially.

That is, some sort of table needs to be maintained, such

that before each read/write to a particular register, a table

look up can be made to verify that the operation can occur.

This is similar to restricted memory areas that can ONLY be

used by kernel procsses, and inaccessible by user processes

-- this is used in all good OSes. Hope that helps.