NickIlieskou Posted April 4, 2014 Report Share Posted April 4, 2014 Hey to everybody, I would like to ask a very simple question just to clarify how the concurrency concept work in SystemC. Let's say that we have two modules. Both modules are sensitive to the positive edge of the simulation clock. module1 is changing the value of a signal (or of a global variable). At the same time module2 has to read the signal ( or the global variable ). So my main question is if in one cycle during which both modules are invoked at the same time module 2 will read the latest value that module1 will output. I think that SystemC has the notion of delta cycle by which before going to the next simulation step ( or clock cycle ) it will make sure that all processes read the latest values of signal/variables independently from which or how many modules have changed their value. Thank you in advance!!! Quote Link to comment Share on other sites More sharing options...
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