SystemC connect to SystemVerilog Interface?

[samng 1]

Hi,

 

I am interested in wrapping a C model with SystemC wrapper to mimic a future RTL design. Is it possible to create a port that can connect directly to a SystemVerilog Interface? For Example:

 

SystemC:

 

struct foo{

   bool valid;

   sc_uint<8> data;

};

 

SC_MODULE (xyz) {

   sc_inout<foo>  port1;

...

};

 

SystemVerilog:

 

interface abc ()

  logic valid;

  logic [7:0] data;

endinterface

 

abc abc_i();

 

xyz (

  .port1(abc_i);

....

);

 

Would this work?

 

Thanks,

Sam

[amitk3553 7]

Hello sam,

 

May be its possible through UVM connect. i donot know much about it, but if u explore it, u can find some solution.

 

 

 

 

 

 

Regards

cam