getvictor Posted December 18, 2013 Report Share Posted December 18, 2013 Your can edit and simulate a simple SystemVerilog design and UVM testbench on EDA Playground: http://www.edaplayground.com/s/example/546No software installation needed.About EDA Playground:EDA Playground is a web browser-based integrated development environment (IDE) for simulation of SystemVerilog, Verilog, VHDL, and other HDLs. EDA Playground is a free web application that allows users to edit, simulate, share, synthesize, and view waves for hardware description language (HDL) code. It is the first online HDL development environment and waveform viewer for the semiconductor industry.EDA Playground homepage: http://www.edaplayground.comEngineers have used EDA Playground for:-- creating hands-on training for students-- demonstrating best practices to other engineers-- asking SystemVerilog questions on online forums-- testing candidates' coding skills during technical interviews (phone and in-person)-- quick prototyping -- trying something before inserting the code into a large code base-- checking whether their RTL syntax/code is synthesizableEDA Playground is actively seeking partners to integrate additional EDA tools. Future tools will include formal verification, linting, and analog and mixed-signal support. Quote Link to comment Share on other sites More sharing options...
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