aynsley Posted June 15, 2010 Report Share Posted June 15, 2010 New article "Easier UVM - for VHDL and Verilog Users" posted on http://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm/. In this article we take a look at UVM by considering how you would use UVM to represent ideas familiar to the Verilog or VHDL users, ideas such as design entities, modules, processes, ports, parameters, generics and configuration. Rather than trying trying to demonstrate all the fancy features of UVM, we will deliberately restrict ourselves to a small, well-behaved subset of the UVM library. Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.