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Easier UVM - for VHDL and Verilog Users

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New article "Easier UVM - for VHDL and Verilog Users" posted on http://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm/.

In this article we take a look at UVM by considering how you would use UVM to represent ideas familiar to the Verilog or VHDL users, ideas such as design entities, modules, processes, ports, parameters, generics and configuration. Rather than trying trying to demonstrate all the fancy features of UVM, we will deliberately restrict ourselves to a small, well-behaved subset of the UVM library.

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