bidir TLM ports

[Logger]

I want to create a master model that performs a non-blocking put to a slave.  Later, I expect the slave to do a blocking put back to the master.  So my master should have a uvm_nonblocking_put_port and a uvm_blocking_put_imp.  I'm trying to figure out if one of those bidir port types includes that combination.  It's kind of hard to decipher the TLM code.

 

Anyone know of example code using the bidir ports?

 

[Logger]

I figured out an example for master and slave ports.  Not exactly what I was looking for, but since I didn't find such an example in the UVM docs I thought I'd post it here for you reading pleasure.

program test;

import uvm_pkg::*;

class Master extends uvm_component;

   uvm_master_port#(uvm_sequence_item) port;

   `uvm_component_utils(Master)

   function new(string name="Master", uvm_component parent=null);
      super.new(name,parent);
      port = new("port",this);
   endfunction // new

   virtual task run_phase(uvm_phase phase);
      uvm_sequence_item item = new("master_item");
      phase.raise_objection(this);

      while (!port.try_put(item)) #10;

      `uvm_info("MASTER", {"Put: ", item.get_name()}, UVM_LOW)

      port.get(item);

      `uvm_info("MASTER", {"Got: ", item.get_name()}, UVM_LOW)

      phase.drop_objection(this);
   endtask // run_phase

endclass // Master


class Slave extends uvm_component;

   uvm_slave_port#(uvm_sequence_item) port;

   `uvm_component_utils(Slave)

   function new(string name="Slave", uvm_component parent=null);
      super.new(name,parent);
      port = new("port",this);
   endfunction // new

   virtual task run_phase(uvm_phase phase);
      uvm_sequence_item item;

      phase.raise_objection(this);

      port.get(item);

      `uvm_info("SLAVE", {"Got: ", item.get_name()}, UVM_LOW)

      #10;

      item = new("slave_item");
      port.put(item);

      `uvm_info("SLAVE", {"Put: ", item.get_name()}, UVM_LOW)

      phase.drop_objection(this);
   endtask // run_phase
endclass // Slave


class Test extends uvm_test;

   Master master;
   Slave slave;
   uvm_tlm_req_rsp_channel#(uvm_sequence_item) chan;

   `uvm_component_utils(Test)

   function new(string name="Test", uvm_component parent=null);
      super.new(name,parent);
      chan = new("chan",this);
   endfunction // new

   virtual function void build_phase(uvm_phase phase);
      master = Master::type_id::create("master",this);
      slave = Slave::type_id::create("slave",this);
   endfunction // build_phase

   virtual function void connect_phase(uvm_phase phase);
      master.port.connect(chan.master_export);
      slave.port.connect(chan.slave_export);
   endfunction // connect_phase

endclass // Test

   initial begin
      run_test("Test");
   end

endprogram // test