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Notify scoreboard about memory accesses

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I have a UVM reg model, with both registers and memories.

Some of them are for the DUT configuration, and some of them are “status” and are read many times during normal operation.


What is the correct way for a scoreboard to be aware of all these accesses?


My reg model uses a uvm_reg_predictor, and I originally wanted to use its analysis port.

Unfortunately, only the register accesses are reported. Memory accesses are not. I even looked in the UVM source code and looks like memories are not yet supported.


Should I convert the memories to pseudo-“registers”?


Thanks, Ofir

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