Problem with ports vector binding

[Fearless_Idiot]

Hello,

for a uni-project I have to describe a 16bit adressing space main memory using structural view. Among others, I have two components (a decoder and a multiplexer) with arrays of 'sc_out<sc_bv<16> >' and 'sc_in<sc_bv<16> >' respectively. I used sc_vector for the declaration of those arrays. I finally use a module called Memory as a container. The compiling works all fine. But when I run the test i wrote for the module it halts at simulation start with this error:

 

Error: (E109) complete binding failed: port not bound: port 'RAM_16.MUX.in_65535' (sc_in)
In file: ../../../../src/sysc/communication/sc_port.cpp:230

 

Is this really related to wrong binding? It seems all well connected to me and I'm really stuck on this problem. I'm attaching the code for the above-mentioned files.

 

//file Decoder_16.hpp
#ifndef DECODER_16_HPP
#define DECODER_16_HPP

#define RAM_SIZE 65536

#include <systemc.h>
#include <iostream>

SC_MODULE(Decoder_16)
{
	sc_in<bool> clock;
   	sc_in<sc_bv<16> > dec_in;
   	sc_vector<sc_out<sc_bv<1> > > dec_out;

   	void route();

   	SC_CTOR(Decoder_16) 
	{
		dec_out.init(RAM_SIZE);

      		SC_METHOD(route); 

      		sensitive << dec_in << clock.pos(); 
		dont_initialize();
   	}

};

#endif

//file Decoder_16.cpp
#include <systemc.h>
#include "Decoder_16.hpp"

//#define RAM_SIZE 65536

using namespace std;

void Decoder_16 :: route()
{
   sc_bv<16> tmp_in =dec_in.read();
   sc_int<64> tmp = tmp_in.to_uint();
   
   for (unsigned j=0;j < RAM_SIZE; j++)
   {
      if (j==tmp)
	dec_out[j].write('1');
      else
        dec_out[j].write('0');
   }
   return;
}

//file Mux_16.hpp
#ifndef MUX_16_HPP
#define MUX_16_HPP

#define RAM_SIZE 65536

#include <systemc.h>
#include <iostream>

SC_MODULE(Mux_16)
{
	sc_in<bool> clock;
   	sc_vector<sc_in<sc_bv<16> > > in;
        sc_in<sc_bv<16> > sel;
   	sc_out<sc_bv<16> > out;
	sc_signal<sc_bv<16> > sel_sig;
	sc_int<64> sel_dec;
	sc_signal<sc_bv<16> > data_sig;

   	void select();

   	SC_CTOR(Mux_16)
	:   in("in"), sel("sel"), out("out")
	{
		//Debug
		cout << endl << "DEBUG:	Entered MUX constructor!" << endl;

		in.init(RAM_SIZE);

      		SC_METHOD(select); 

      		sensitive << sel << clock.pos();
		dont_initialize();
   	}

};

#endif

//file Mux_16.cpp
#include <systemc.h>
#include "Mux_16.hpp"

//#define RAM_SIZE 65536

using namespace std;

void Mux_16 :: select()
{
   sel_sig = sel.read();
   sel_dec = sel_sig.read().to_uint();
   data_sig = in[sel_dec].read();
   out.write(data_sig);

   return;
}

//file Memory_16b_RISC.hpp
#ifndef MEMORY_16B_RISC
#define MEMORY_16B_RISC


#define RAM_SIZE 65536

#include <systemc.h>
#include <iostream>
#include "Decoder_16.hpp"
#include "Cell.hpp"
#include "And_1.hpp"
#include "Mux_16.hpp"


SC_MODULE(Memory_16b_RISC){

	//Declaration of the inputs
	sc_in<bool> clock;
	sc_in<sc_bv<16> > addr;				//input address <--- ALU output
	sc_in<sc_bv<16> > data_in;			//input data <--- register file 'src2' output.
	sc_in<sc_bv<1> > write_en;			//memory write enable <--- control unit 'we_dmem' output.
	sc_in<sc_bv<1> > read_en;			//memory read enable <--- control unit 're_dmem' output.

	//Declaration of the outputs
	sc_out<sc_bv<16> > data_out;			//output data ---> Multiplexer_3_2 'in3' input. 

	//Signals Declaration
	sc_vector<sc_signal<sc_bv<1> > > sel_bit;
	sc_vector<sc_signal<sc_bv<1> > > read_line;
        sc_vector<sc_signal<sc_bv<1> > > write_line;
        sc_vector<sc_signal<sc_bv<16> > > mux_data_in;


	//Methods Declaration
        void Run();

	//Submodules Declaration
	sc_vector<Cell> MemCell;
	sc_vector<And_1> read_and;
	sc_vector<And_1> write_and;
	Decoder_16 dec16;
        Mux_16 mux16;

	//Constructor
	SC_CTOR(Memory_16b_RISC) 
	   :   MemCell("M1", RAM_SIZE), read_and("A1", RAM_SIZE), write_and("A2", RAM_SIZE), dec16("DEC"), mux16("MUX")
	{
		//Debug
		cout << endl << "DEBUG:	Entered memory constructor!" << endl;

		sel_bit.init(RAM_SIZE);
		read_line.init(RAM_SIZE);
		write_line.init(RAM_SIZE);
		mux_data_in.init(RAM_SIZE);

		SC_METHOD(Run);
			sensitive << clock.pos();
			dont_initialize();
	}	

	//~Memory_16b_RISC();

};//End of Memory Module

#endif

//file Memory_16b_RISC.cpp
#include <systemc.h>
#include <iostream>
#include "Memory_16b_RISC.hpp"

using namespace std;

void Memory_16b_RISC :: Run()
{
	//Debug
	cout << endl << "DEBUG:	Run() has been called!" << endl;

	//Decoder gate port map
	dec16.clock(clock);
	dec16.dec_in(addr);
	dec16.dec_out.bind(sel_bit);

        //Multiplexer gate port map
	mux16.clock(clock);
        mux16.sel(addr);
        mux16.out(data_out);
	mux16.in.bind(mux_data_in);

	for (unsigned i=0; i<RAM_SIZE; i++)
	{
		//Debug
		cout << endl << "DEBUG:	Entered memory mapping cycle!" << endl;

		//Cell port map
		MemCell.at(i).clock(clock);
		MemCell.at(i).wr_en(write_line.at(i));
		MemCell.at(i).re_en(read_line.at(i));
		MemCell.at(i).din(data_in);
		MemCell.at(i).dout(mux_data_in.at(i));

		//Reading AND gate port map
		read_and.at(i).clock(clock);
		read_and.at(i).in1(read_en);
		read_and.at(i).in2(sel_bit.at(i));
		read_and.at(i).out1(read_line.at(i));

		//Writing AND gate port map
		write_and.at(i).clock(clock);
		write_and.at(i).in1(write_en);
		write_and.at(i).in2(sel_bit.at(i));
		write_and.at(i).out1(write_line.at(i));
	}

	return;
}

I can also provide code for the stimulus generation and for the test if that is needed for debugging. Thanks in advance for your help. Bear in mind that I come from vhdl training and I'm still kind of self-training in systemc after taking a course in c++ programming, so don't be too harsh on me : )

 

[Fearless_Idiot]

UPDATE: Resolved the issue myself! I had written the port map instructions in the module method. So at simulation start they weren't really yet mapped... What a dumb mistake

Sorry to bother you.