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Showing results for tags 'sc_vector ports components'.
Hello, for a uni-project I have to describe a 16bit adressing space main memory using structural view. Among others, I have two components (a decoder and a multiplexer) with arrays of 'sc_out<sc_bv<16> >' and 'sc_in<sc_bv<16> >' respectively. I used sc_vector for the declaration of those arrays. I finally use a module called Memory as a container. The compiling works all fine. But when I run the test i wrote for the module it halts at simulation start with this error: Error: (E109) complete binding failed: port not bound: port 'RAM_16.MUX.in_65535' (sc_in) In file